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authorSubrata Banik <subrata.banik@intel.com>2019-04-10 11:36:58 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-04-13 03:25:35 +0000
commit459df6697a150e0be5dd0378d98ef54eff520641 (patch)
tree9887e2663c3af03b4f84e881ac9a55b70c500a17 /src/soc/intel
parentc47eda0e6be36fe7b8c77ff5d41db8d240cf67fd (diff)
downloadcoreboot-459df6697a150e0be5dd0378d98ef54eff520641.tar.xz
soc/intel/cpulib: Factor out IA32_PERF_CTL (0x199) MSR code
This patch replaces multiple IA32_PERF_CTL programming with single helper function. TEST=Build and boot WHL and CML platform. Change-Id: I212daa61aa11191dd832630461b517d3dbedd6e1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index c847390d40..9964f2b02c 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -73,6 +73,13 @@ int cpu_config_tdp_levels(void)
return (platform_info.hi >> 1) & 3;
}
+static void set_perf_control_msr(msr_t msr)
+{
+ wrmsr(IA32_PERF_CTL, msr);
+ printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
+ ((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+}
+
/*
* TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
* factory configured values for of 1-core, 2-core, 3-core
@@ -93,9 +100,7 @@ void cpu_set_p_state_to_turbo_ratio(void)
perf_ctl.lo = (msr.lo & 0xff) << 8;
perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
- printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+ set_perf_control_msr(perf_ctl);
}
/*
@@ -113,9 +118,7 @@ void cpu_set_p_state_to_nominal_tdp_ratio(void)
perf_ctl.lo = (msr.lo & 0xff) << 8;
perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
- printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+ set_perf_control_msr(perf_ctl);
}
/*
@@ -133,9 +136,7 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void)
perf_ctl.lo = msr.lo & 0xff00;
perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
- printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ);
+ set_perf_control_msr(perf_ctl);
}
/*
@@ -152,9 +153,8 @@ void cpu_set_p_state_to_min_clock_ratio(void)
min_ratio = cpu_get_min_ratio();
perf_ctl.lo = (min_ratio << 8) & 0xff00;
perf_ctl.hi = 0;
- wrmsr(IA32_PERF_CTL, perf_ctl);
- printk(BIOS_DEBUG, "CPU: frequency set to %u MHz\n",
- (min_ratio * CONFIG_CPU_BCLK_MHZ));
+
+ set_perf_control_msr(perf_ctl);
}
/*