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authorSubrata Banik <subrata.banik@intel.com>2017-05-12 11:29:43 +0530
committerMartin Roth <martinroth@google.com>2017-05-16 17:44:24 +0200
commit481b364222322b96dc16ebc126040ed9c0aa2811 (patch)
tree4ce28da4942f89923b38f4c428b7ea4e923d8657 /src/soc/intel
parent7bde848d625d078f15a77bf7ed53613789c0daf8 (diff)
downloadcoreboot-481b364222322b96dc16ebc126040ed9c0aa2811.tar.xz
soc/intel/skylake: Configure C-state interrupt response time
Program C3/C7/C10 interrupt response time for all cores. Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/cpu.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 2f356355b0..c472617b0f 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -360,6 +360,44 @@ static void configure_mca(void)
}
}
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ /* C-state Interrupt Response Latency Control 0 - package C3 latency */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);
+
+ /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);
+
+ /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
+
+ /* C-state Interrupt Response Latency Control 3 - package C8 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS |
+ C_STATE_LATENCY_CONTROL_3_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
+
+ /* C-state Interrupt Response Latency Control 4 - package C9 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS |
+ C_STATE_LATENCY_CONTROL_4_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
+
+ /* C-state Interrupt Response Latency Control 5 - package C10 */
+ msr.hi = 0;
+ msr.lo = IRTL_VALID | IRTL_1024_NS |
+ C_STATE_LATENCY_CONTROL_5_LIMIT;
+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+}
+
/* All CPUs including BSP will run the following function. */
static void cpu_core_init(device_t cpu)
{
@@ -370,6 +408,9 @@ static void cpu_core_init(device_t cpu)
enable_lapic_tpr();
setup_lapic();
+ /* Configure c-state interrupt response time */
+ configure_c_states();
+
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();