summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorMeera Ravindranath <meera.ravindranath@intel.com>2019-12-12 10:37:49 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-12-31 15:17:27 +0000
commit48c7870e5294336851472ac9eb1e4665715316f9 (patch)
tree59ada180ddfdbb88c2b295303bfec94404553a9e /src/soc/intel
parent408d1dac9e23250c0e485bbf934771f769b717c1 (diff)
downloadcoreboot-48c7870e5294336851472ac9eb1e4665715316f9.tar.xz
soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/acpi.c18
-rw-r--r--src/soc/intel/icelake/acpi.c18
-rw-r--r--src/soc/intel/tigerlake/acpi.c18
3 files changed, 24 insertions, 30 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 6846594ebf..6d1970bafa 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -179,16 +179,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
const struct soc_intel_cannonlake_config *config;
config = config_of_soc();
- if (!config->PmTimerDisabled) {
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->pm_tmr_len = 4;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
- }
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ fadt->pm_tmr_len = 4;
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 4089679d1c..728cfb148f 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -172,16 +172,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
config_t *config = config_of_soc();
- if (!config->PmTimerDisabled) {
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->pm_tmr_len = 4;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
- }
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ fadt->pm_tmr_len = 4;
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 225f4e8211..5e04c9a3b5 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -171,16 +171,14 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
config_t *config = config_of_soc();
- if (!config->PmTimerDisabled) {
- fadt->pm_tmr_blk = pmbase + PM1_TMR;
- fadt->pm_tmr_len = 4;
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.access_size = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
- fadt->x_pm_tmr_blk.addrh = 0x0;
- }
+ fadt->pm_tmr_blk = pmbase + PM1_TMR;
+ fadt->pm_tmr_len = 4;
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;