diff options
author | Andrey Petrov <andrey.petrov@intel.com> | 2016-03-02 15:09:27 -0800 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-03-08 17:28:45 +0100 |
commit | 491c016d77fa56461e8669e45796da97bbab3c37 (patch) | |
tree | ac58ec3ae89b0cd5a57812afa22f2b8ec6d32725 /src/soc/intel | |
parent | 41aa8bc9abd8ce29a716d283c481fd74e9ac9567 (diff) | |
download | coreboot-491c016d77fa56461e8669e45796da97bbab3c37.tar.xz |
soc/intel/apollolake: Add cbmem_top() implementation
On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.
Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 2 | ||||
-rw-r--r-- | src/soc/intel/apollolake/memmap.c | 27 | ||||
-rw-r--r-- | src/soc/intel/apollolake/placeholders.c | 5 |
3 files changed, 29 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 81ca688d67..dd2213e869 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -20,12 +20,14 @@ romstage-y += placeholders.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c new file mode 100644 index 0000000000..bfff9652da --- /dev/null +++ b/src/soc/intel/apollolake/memmap.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/pci.h> +#include <soc/northbridge.h> +#include <soc/pci_devs.h> + +static uintptr_t smm_region_start(void) +{ + return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index 3a818eb1e3..808bd5490b 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -3,11 +3,6 @@ #include <delay.h> #include <rules.h> -void *cbmem_top(void) -{ - return NULL; -} - void southbridge_smi_set_eos(void) { } |