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authorTim Chen <tim-chen@quanta.corp-partner.google.com>2020-04-29 13:56:37 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:27:14 +0000
commit4c7bc8db749ffaf0bb3a54b43b0a56652285cde9 (patch)
treecd7f335358b268838dcd926c607d8289368afec1 /src/soc/intel
parent52e56e84796d8b4def9341f2302b355f059added (diff)
downloadcoreboot-4c7bc8db749ffaf0bb3a54b43b0a56652285cde9.tar.xz
mb/google/hatch/vr/puff: Add psys_pmax calculation
This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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