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authorAaron Durbin <adurbin@chromium.org>2018-04-10 09:24:54 -0600
committerAaron Durbin <adurbin@chromium.org>2018-04-10 18:07:54 +0000
commit551e4be7301eca04104c8f0d4379b906dfb07c1b (patch)
tree5d7183a8863fadfe1ff2f1a4c556c9ae69e3419d /src/soc/intel
parent6d61db0d2cec4a3b141da77bcf5675b8b154c8b7 (diff)
downloadcoreboot-551e4be7301eca04104c8f0d4379b906dfb07c1b.tar.xz
soc/intel/common: prepare for lpss clock split
Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/Kconfig4
-rw-r--r--src/soc/intel/cannonlake/Kconfig4
-rw-r--r--src/soc/intel/common/Kconfig7
-rw-r--r--src/soc/intel/common/block/gspi/Kconfig8
-rw-r--r--src/soc/intel/common/block/gspi/gspi.c3
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpss.h4
-rw-r--r--src/soc/intel/skylake/Kconfig4
7 files changed, 18 insertions, 16 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fcb1ef757f..19185eb411 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -159,13 +159,13 @@ config CPU_ADDR_BITS
int
default 36
-config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 133
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
- default SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+ default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index fc73210f75..6f4029509c 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -186,13 +186,13 @@ config SOC_INTEL_CANNONLAKE_LPDDR4_INIT
bool
default n
-config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 120
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
- default SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+ default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index c4e6514b85..6df62b633d 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -30,13 +30,6 @@ config ACPI_CONSOLE
help
Provide a mechanism for serial console based ACPI debug.
-config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
- int
- help
- The clock speed that the controllers in LPSS(GSPI, I2C) are running
- at, in MHz. No default is set here as this is an SOC-specific value
- and must be provided by the SOC.
-
config MMA
bool "Enable MMA (Memory Margin Analysis) support for Intel Core"
default n
diff --git a/src/soc/intel/common/block/gspi/Kconfig b/src/soc/intel/common/block/gspi/Kconfig
index 8fa847a1b8..d2776ca1a4 100644
--- a/src/soc/intel/common/block/gspi/Kconfig
+++ b/src/soc/intel/common/block/gspi/Kconfig
@@ -3,6 +3,14 @@ config SOC_INTEL_COMMON_BLOCK_GSPI
help
Intel Processor Common GSPI support
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
+ int
+ depends on SOC_INTEL_COMMON_BLOCK_GSPI
+ help
+ The input clock speed into the SPI controller IP block, in MHz.
+ No default is set here as this is an SOC-specific value
+ and must be provided by the SOC.
+
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
depends on SOC_INTEL_COMMON_BLOCK_GSPI
diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 60c7391ad0..e4e44c22bb 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -380,7 +380,8 @@ static void gspi_cs_deassert(const struct spi_slave *dev)
static uint32_t gspi_get_clk_div(unsigned int gspi_bus)
{
- const uint32_t ref_clk_mhz = CONFIG_SOC_INTEL_COMMON_LPSS_CLOCK_MHZ;
+ const uint32_t ref_clk_mhz =
+ CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ;
const uint32_t gspi_clk_mhz = gspi_get_bus_clk_mhz(gspi_bus);
assert(gspi_clk_mhz != 0);
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index c6caae2675..ca5568996f 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -22,8 +22,8 @@
void lpss_reset_release(uintptr_t base);
/*
- * Update clock divider parameters. Clock frequency is
- * configured as SOC_INTEL_COMMON_LPSS_CLOCK_MHZ * (M / N)
+ * Update clock divider parameters. Clock frequency is dependent on source
+ * clock frequency of each IP block. Resulting clock will be src_freq * (M / N).
*/
void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index cf947a7670..326b84722a 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -338,13 +338,13 @@ config NO_FADT_8042
help
Choose this option if you want to disable 8042 Keyboard
-config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
int
default 120
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
- default SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
+ default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int