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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-30 14:16:10 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-31 22:03:39 +0200 |
| commit | 56c99f28501bbb79a9f8b7a1e1bd698788b42f0e (patch) | |
| tree | a3d802d1b017bcdf7dcbf433d70d16e3d60a141a /src/soc/intel | |
| parent | ca65bb7b4e9247362e8667d5833119ffffa82321 (diff) | |
| download | coreboot-56c99f28501bbb79a9f8b7a1e1bd698788b42f0e.tar.xz | |
soc/intel/quark: Set temporary I2C base address
Set a temporary I2C base address during romstage.
TEST=Build and run on Galileo Gen2
Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/quark/include/soc/iomap.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index 61773d5d4c..1224bcc156 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -25,7 +25,8 @@ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE /* I2C/GPIO Controller */ -#define I2C_GPIO_BASE_ADDRESS 0xa0020000 +#define I2C_BASE_ADDRESS 0xa0020000 +#define GPIO_BASE_ADDRESS 0xa0021000 /* * I/O port address space diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c4f9844754..c86c2eae3d 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -52,7 +52,8 @@ static const struct reg_script legacy_gpio_init[] = { static const struct reg_script i2c_gpio_controller_init[] = { /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_SCRIPT_END }; |