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authorJulien Viard de Galbert <jviarddegalbert@online.net>2018-02-08 14:03:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-05-14 21:03:43 +0000
commit5a1f5400fb93ffc257486318351feff9c3b48d21 (patch)
tree9f8ae9164deddbcad6af2dbed463bd8fe58bb51e /src/soc/intel
parentf729cd0b40719e41bc6d337b179b1a36f775b00e (diff)
downloadcoreboot-5a1f5400fb93ffc257486318351feff9c3b48d21.tar.xz
soc/intel/denverton_ns: Enable common code for CPU
Change-Id: Ib215aa17dd20112946b74a1b63ce8a735388873c Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/24927 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/denverton_ns/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index d666bcc88c..35296d553d 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS
select PCR_COMMON_IOSF_1_0
select SMP
select SOC_INTEL_COMMON_BLOCK
+ select SOC_INTEL_COMMON_BLOCK_CPU
# select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_FAST_SPI
select SOC_INTEL_COMMON_BLOCK_GPIO
@@ -117,6 +118,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x0ff80
+config CPU_BCLK_MHZ
+ int
+ default 100
+
config SMM_TSEG_SIZE
hex
default 0x200000