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authorSubrata Banik <subrata.banik@intel.com>2017-11-07 16:10:05 +0530
committerAaron Durbin <adurbin@chromium.org>2017-11-11 18:19:15 +0000
commit6c4b5916fcd4844410a709320ab7bf5a06a45596 (patch)
tree27874455b3a10d43d478eca05fa8fecb35716842 /src/soc/intel
parentf79b636088d36f1a6ac58f02e58ad8561899bb31 (diff)
downloadcoreboot-6c4b5916fcd4844410a709320ab7bf5a06a45596.tar.xz
soc/intel/common/block: Add Intel common SPI support
SOC need to select specific macros need to compile common SPI code. Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/spi.h37
-rw-r--r--src/soc/intel/common/block/spi/Kconfig4
-rw-r--r--src/soc/intel/common/block/spi/Makefile.inc13
-rw-r--r--src/soc/intel/common/block/spi/spi.c76
4 files changed, 130 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/spi.h b/src/soc/intel/common/block/include/intelblocks/spi.h
new file mode 100644
index 0000000000..e652a369d8
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/spi.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_SPI_H
+#define SOC_INTEL_COMMON_BLOCK_SPI_H
+
+/*
+ * SoC overrides
+ *
+ * All new SoC must implement below functionality.
+ */
+
+/* Function to convert input device function to bus number
+ * Input: Device Function number
+ * Output: -1 translate to Error, >=0 is bus number
+ */
+int spi_soc_devfn_to_bus(unsigned int devfn);
+
+/* Function to convert input bus number to device function
+ * Input: Bus number
+ * Output: -1 translate to Error, >=0 is function number
+ */
+int spi_soc_bus_to_devfn(unsigned int bus);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_SPI_H */
diff --git a/src/soc/intel/common/block/spi/Kconfig b/src/soc/intel/common/block/spi/Kconfig
new file mode 100644
index 0000000000..57677630cd
--- /dev/null
+++ b/src/soc/intel/common/block/spi/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_SPI
+ bool
+ help
+ Intel Processor common SPI support
diff --git a/src/soc/intel/common/block/spi/Makefile.inc b/src/soc/intel/common/block/spi/Makefile.inc
new file mode 100644
index 0000000000..1ac4c2175b
--- /dev/null
+++ b/src/soc/intel/common/block/spi/Makefile.inc
@@ -0,0 +1,13 @@
+ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_SPI),y)
+bootblock-y += spi.c
+
+verstage-y += spi.c
+
+romstage-y += spi.c
+
+ramstage-y += spi.c
+
+postcar-y += spi.c
+
+smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
+endif
diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c
new file mode 100644
index 0000000000..9a34044adb
--- /dev/null
+++ b/src/soc/intel/common/block/spi/spi.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/spi.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/spi.h>
+#include <soc/pci_devs.h>
+#include <spi-generic.h>
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+ { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },
+#if !ENV_SMM && IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI)
+ { .ctrlr = &gspi_ctrlr, .bus_start = 1,
+ .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},
+#endif
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
+
+static int spi_dev_to_bus(struct device *dev)
+{
+ return spi_soc_devfn_to_bus(dev->path.pci.devfn);
+}
+
+static struct spi_bus_operations spi_bus_ops = {
+ .dev_to_bus = &spi_dev_to_bus,
+};
+
+static struct device_operations spi_dev_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .scan_bus = &scan_generic_bus,
+ .ops_spi_bus = &spi_bus_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_SPT_SPI1,
+ PCI_DEVICE_ID_INTEL_SPT_SPI2,
+ PCI_DEVICE_ID_INTEL_SPT_SPI3,
+ PCI_DEVICE_ID_INTEL_APL_SPI0,
+ PCI_DEVICE_ID_INTEL_APL_SPI1,
+ PCI_DEVICE_ID_INTEL_APL_SPI2,
+ PCI_DEVICE_ID_INTEL_APL_HWSEQ_SPI,
+ PCI_DEVICE_ID_INTEL_GLK_SPI0,
+ PCI_DEVICE_ID_INTEL_GLK_SPI1,
+ PCI_DEVICE_ID_INTEL_GLK_SPI2,
+ PCI_DEVICE_ID_INTEL_CNL_SPI0,
+ PCI_DEVICE_ID_INTEL_CNL_SPI1,
+ PCI_DEVICE_ID_INTEL_CNL_SPI2,
+ PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,
+ 0
+};
+
+static const struct pci_driver pch_spi __pci_driver = {
+ .ops = &spi_dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};