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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-07 09:04:46 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-09 18:45:44 +0200
commit6ec72c9b4f4a903d9a451bc17629e679399aa9ee (patch)
tree815f70ba90e3646911d8380d803c823f1fefb507 /src/soc/intel
parent148762110c8a00c88b8e0326ec69dc7392bf3739 (diff)
downloadcoreboot-6ec72c9b4f4a903d9a451bc17629e679399aa9ee.tar.xz
drivers/uart: Use uart_platform_refclk for all UART models
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/uart_early.c6
-rw-r--r--src/soc/intel/quark/Kconfig1
-rw-r--r--src/soc/intel/skylake/uart_debug.c11
3 files changed, 1 insertions, 17 deletions
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index e8dfeda565..0e530609bd 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -68,12 +68,6 @@ uintptr_t uart_platform_base(int idx)
return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
}
-unsigned int uart_platform_refclk(void)
-{
- /* That's within 0.5% of the actual value we've set earlier */
- return 115200 * 16;
-}
-
static const struct pad_config uart_gpios[] = {
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index ae25c328c6..6a2349fb8d 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON
select SOC_SETS_MTRRS
select TSC_CONSTANT_RATE
+ select UART_OVERRIDE_REFCLK
select UDELAY_TSC
select UNCOMPRESSED_RAMSTAGE
select USE_MARCH_586
diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c
index c463bea145..f3d576b3aa 100644
--- a/src/soc/intel/skylake/uart_debug.c
+++ b/src/soc/intel/skylake/uart_debug.c
@@ -18,17 +18,6 @@
#include <soc/iomap.h>
#include <soc/serialio.h>
-unsigned int uart_platform_refclk(void)
-{
- /*
- * Set M and N divisor inputs and enable clock.
- * Main reference frequency to UART is:
- * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
- * The different order below is to handle integer math overflow.
- */
- return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
-}
-
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2