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| author | Martin Roth <gaumless@gmail.com> | 2014-05-12 21:52:54 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-05-29 23:09:12 +0200 |
| commit | 7312c54dc684099a6d85ae13f3de097754ced0f0 (patch) | |
| tree | 9042b9a10d9202330048f6ea31872e2ae7d6b7a1 /src/soc/intel | |
| parent | 2c55b70d1a9a52060708ee0cf44eac9c2764ddd4 (diff) | |
| download | coreboot-7312c54dc684099a6d85ae13f3de097754ced0f0.tar.xz | |
add rtc_init() to romstage
The FSP clears the bit that tells us whether or not the RTC has lost
power when it sets up memory. Because of this, we need to initialize
the RTC in romstage instead of ramstage.
Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5735
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions