diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-14 12:18:38 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-21 19:46:43 +0000 |
| commit | 7a357eb8657fd891aad33fd710d2f9d4d80c9130 (patch) | |
| tree | 0b340a5a9c948512dace2f2ff963161629b18e83 /src/soc/intel | |
| parent | 53d68b4ffb9f99f51a3634c263b8a9176d7ea1a6 (diff) | |
| download | coreboot-7a357eb8657fd891aad33fd710d2f9d4d80c9130.tar.xz | |
soc/intel/skylake: Fix SGX init sequence
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index a7745cec91..031a01de66 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -437,8 +437,8 @@ void soc_core_init(device_t cpu) /* Enable Turbo */ enable_turbo(); - /* Configure SGX */ - sgx_configure(); + /* Configure Core PRMRR for SGX. */ + prmrr_core_configure(); } static int adjust_apic_id(int index, int apic_id) @@ -472,6 +472,8 @@ static void post_mp_init(void) #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) smm_lock(); #endif + + mp_run_on_all_cpus(sgx_configure, 2000); } static const struct mp_ops mp_ops = { @@ -498,14 +500,6 @@ void soc_init_cpus(struct bus *cpu_bus) /* Thermal throttle activation offset */ configure_thermal_target(); - - /* - * TODO: somehow calling configure_sgx() in cpu_core_init() is not - * successful on the BSP (other threads are fine). Have to run it again - * here to get SGX enabled on BSP. This behavior needs to root-caused - * and we shall not have this redundant call. - */ - sgx_configure(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |