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authorBarnali Sarkar <barnali.sarkar@intel.com>2016-08-03 12:15:22 +0530
committerMartin Roth <martinroth@google.com>2016-08-08 18:24:04 +0200
commit8f2f22d25806a4547be1a1a125f153bb4b0fe581 (patch)
tree959268d99a149b80ec4d4dde38ec5da63a3749f6 /src/soc/intel
parent0dddcd76d74274715b0472ca41ddac88a5203b84 (diff)
downloadcoreboot-8f2f22d25806a4547be1a1a125f153bb4b0fe581.tar.xz
skylake/devicetree: Add PIRQ Routing programming
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/skylake/chip.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index eec6f1ed17..a4dee51b39 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -24,6 +24,7 @@
#include <stdint.h>
#include <soc/gpio_defs.h>
#include <soc/gpe.h>
+#include <soc/irq.h>
#include <soc/intel/common/lpss_i2c.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>