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authorLijian Zhao <lijian.zhao@intel.com>2018-02-15 17:11:00 -0800
committerPatrick Georgi <pgeorgi@google.com>2018-02-22 09:58:39 +0000
commit9672b540874bf3a27df0b35ae94ada32e5a8c601 (patch)
tree688015ba85ad7e4306cad2a97d12daff3894c0ad /src/soc/intel
parent206821ee2f4ecae68fb292d0075bb82acac0c8bb (diff)
downloadcoreboot-9672b540874bf3a27df0b35ae94ada32e5a8c601.tar.xz
soc/intel/cannonlake: Add emmc/sdc port id
EMMC and SD Controller port id listed here, the port id definition came from Cannonlake BIOS Writer Guide 570374. BUG=None TEST=None Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23789 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/include/soc/pcr_ids.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
index 04ea147f38..891b18742b 100644
--- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h
@@ -18,6 +18,8 @@
/*
* Port ids
*/
+#define PID_EMMC 0x52
+#define PID_SDX 0x53
#define PID_GPIOCOM4 0x6a
#define PID_GPIOCOM3 0x6b
#define PID_GPIOCOM2 0x6c