diff options
author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-06-06 14:29:53 +0530 |
---|---|---|
committer | Duncan Laurie <dlaurie@chromium.org> | 2017-07-01 08:49:11 +0000 |
commit | a1de1a0810892c3c3a22ed6e2868fbef3bde8134 (patch) | |
tree | 3a1a3b0b9add420797d1b6ed149718ecc5653ae3 /src/soc/intel | |
parent | 9692f31a4f63f5f558466b1e88f3557259e703dd (diff) | |
download | coreboot-a1de1a0810892c3c3a22ed6e2868fbef3bde8134.tar.xz |
soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignment
This patch basically does two things -
1) Remove unnecessary setting of flex_ratio to TDP nominal:
Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured
in MSR_PLATFORM_INFO(0xCE).
If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done
using MSR_FLEX_RATIO (0x194).
Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal
Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is
actually less than the factory configured Maximum Non TURBO Ratio (P1).
So, this code is actually not required.
Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor.
This Bit implies Processor Boot Max Frequency -
0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default)
This setting determines if the processor will operate at maximum frequency
at power-on and boot.
Thus this patch will avoid one extra platform warm reset now onwards.
2) Remove wrongly setting Max Frequency in Bootblock phase:
In the function set_max_frequency(), the P-State max ratio was set to
TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non
Trbo ratio.
But, when the cpu gets reset, it will operate with the Max-Non Turbo
ratio only, which is greater than the TDP Nominal ratio.
So, no need to set back the ratio to TDP Nominal which is lower than
the currently operating frequency.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 1 | ||||
-rw-r--r-- | src/soc/intel/skylake/bootblock/cpu.c | 73 | ||||
-rw-r--r-- | src/soc/intel/skylake/include/soc/bootblock.h | 1 |
3 files changed, 0 insertions, 75 deletions
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index cbe3dd2fdc..058cec855b 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -47,7 +47,6 @@ void bootblock_soc_init(void) * and abase, i2c programming and print platform info */ report_platform_info(); - set_max_freq(); pch_early_init(); gspi_early_bar_init(); diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 4a5bf08042..0f3038dabf 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -14,84 +14,11 @@ * GNU General Public License for more details. */ -#include <cpu/x86/msr.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> -#include <intelblocks/msr.h> -#include <reset.h> #include <soc/bootblock.h> -/* Soft Reset Data Register Bit 12 = MAX Boot Frequency */ -#define SPI_STRAP_MAX_FREQ (1<<12) -/* Soft Reset Data Register Bit 6-11 = Flex Ratio */ -#define FLEX_RATIO_BIT 6 - -static void set_pch_cpu_strap(u8 flex_ratio) -{ - u32 soft_reset_data; - - /* Soft Reset Data Register Bit 12 = MAX Boot Frequency - * Bit 6-11 = Flex Ratio - * Soft Reset Data register located at SPIBAR0 offset 0xF8[0:15]. - */ - soft_reset_data = SPI_STRAP_MAX_FREQ; - soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT); - fast_spi_set_strap_msg_data(soft_reset_data); -} - -static void set_flex_ratio_to_tdp_nominal(void) -{ - msr_t flex_ratio, msr; - u8 nominal_ratio; - - /* Check for Flex Ratio support */ - flex_ratio = rdmsr(MSR_FLEX_RATIO); - if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; - - /* Check for >0 configurable TDPs */ - msr = rdmsr(MSR_PLATFORM_INFO); - if (((msr.hi >> 1) & 3) == 0) - return; - - /* Use nominal TDP ratio for flex ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - nominal_ratio = msr.lo & 0xff; - - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - - /* Set flex ratio to nominal TDP ratio */ - flex_ratio.lo &= ~0xff00; - flex_ratio.lo |= nominal_ratio << 8; - flex_ratio.lo |= FLEX_RATIO_LOCK; - wrmsr(MSR_FLEX_RATIO, flex_ratio); - - /* Set PCH Soft Reset Data Register with new Flex Ratio */ - set_pch_cpu_strap(nominal_ratio); - - /* Delay before reset to avoid potential TPM lockout */ - mdelay(30); - - /* Issue soft reset, will be "CPU only" due to soft reset data */ - soft_reset(); -} - void bootblock_cpu_init(void) { fast_spi_cache_bios_region(); - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); -} - -void set_max_freq(void) -{ - if (cpu_config_tdp_levels()) - /* Set to nominal TDP ratio */ - cpu_set_p_state_to_nominal_tdp_ratio(); - else - /* Set to max non Turbo ratio */ - cpu_set_p_state_to_max_non_turbo_ratio(); } diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index 10c8de1241..62dd234db4 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -35,6 +35,5 @@ void pch_early_init(void); void pch_early_iorange_init(void); void report_platform_info(void); void report_memory_config(void); -void set_max_freq(void); #endif |