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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 22:48:35 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 21:00:30 +0100 |
| commit | bfca67078cfddc18994fa6bbe9094a2ecca275a3 (patch) | |
| tree | d251389ecf692dab90b16af9dfe643fd1b71386e /src/soc/intel | |
| parent | de01136484c58d13457ccf1e42fdb2310f3cbe65 (diff) | |
| download | coreboot-bfca67078cfddc18994fa6bbe9094a2ecca275a3.tar.xz | |
intel/sandybridge post-car: Redo MTRR settings and stack selection
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Also fixes regression of slower S3 resume path after commit
9b99152 intel/sandybridge: Use common ACPI S3 recovery
Skipping low memory backup and using stage cache for ramstage decreases
time spent on S3 resume path by 50 ms on samsung/lumpy.
Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15790
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions