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authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-24 17:02:08 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-29 10:28:02 +0000
commitc332a47c54f6e9b025a36e14eb0d3b115400d21c (patch)
tree7bf41db0fcb69719ec7c54ee2c36ea4437c37b99 /src/soc/intel
parent03b20350e39c46b141a2f033332b459ab2d4e3d6 (diff)
downloadcoreboot-c332a47c54f6e9b025a36e14eb0d3b115400d21c.tar.xz
soc/intel/tigerlake: Disable image clocks
TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 6ed3dcd2de..9c105cadc2 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -102,6 +102,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
+ /* Image clock: disable all clocks for bypassing FSP pin mux */
+ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
+
/* Enable Hyper Threading */
m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */