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authorFurquan Shaikh <furquan@google.com>2016-05-04 16:03:36 -0700
committerFurquan Shaikh <furquan@google.com>2016-05-06 06:52:28 +0200
commitc681409a8a3429c8aa8572ce18f4560fecb0c0ae (patch)
treea43f622d9693a2af4974fd8c4be65494f6644bc8 /src/soc/intel
parentd264b46c4971f952ce88f66bb147816f5e1dc67d (diff)
downloadcoreboot-c681409a8a3429c8aa8572ce18f4560fecb0c0ae.tar.xz
soc/intel/apollolake: Correct PCI write size in romstage
1. PCI command reg write should be 16-bit. 2. HPTC reg write should be 8-bit. Also, use macros instead of hard-coded values. Currently, the macros are defined in romstage.c, but if more P2SB macros are added, it would be good to move them to a separate header file. Change-Id: Iad1eb6a95467a41ecf454092808d357425c4c2fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14613 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/romstage.c20
1 files changed, 18 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 6b49bbd961..8ec94a7cb3 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -44,6 +44,21 @@
static struct chipset_power_state power_state CAR_GLOBAL;
+/* High Performance Event Timer Configuration */
+#define P2SB_HPTC 0x60
+#define P2SB_HPTC_ADDRESS_ENABLE (1 << 7)
+/*
+ * ADDRESS_SELECT ENCODING_RANGE
+ * 0 0xFED0 0000 - 0xFED0 03FF
+ * 1 0xFED0 1000 - 0xFED0 13FF
+ * 2 0xFED0 2000 - 0xFED0 23FF
+ * 3 0xFED0 3000 - 0xFED0 33FF
+ */
+#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
+
/*
* Enables several BARs and devices which are needed for memory init
* - MCH_BASE_ADDR is needed in order to talk to the memory controller
@@ -65,12 +80,13 @@ static void soc_early_romstage_init(void)
pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */
pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
- pci_write_config32(pmc, PCI_COMMAND,
+ pci_write_config16(pmc, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
/* Enable decoding for HPET. Needed for FSP global pointer storage */
- pci_write_config32(P2SB_DEV, 0x60, 1<<7);
+ pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
+ P2SB_HPTC_ADDRESS_ENABLE);
}
static void disable_watchdog(void)