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authorAndrey Petrov <andrey.petrov@intel.com>2016-04-12 17:00:52 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-13 16:08:47 +0200
commitc6ee58c790dd6f55b0be83c65fd823f88f4cba91 (patch)
tree2c1581116fbb024e080dc975423e206812ec8b01 /src/soc/intel
parent399332d2710137d4a5ca1b9cc2b0416a5291949c (diff)
downloadcoreboot-c6ee58c790dd6f55b0be83c65fd823f88f4cba91.tar.xz
soc/intel/apollolake: Add tsc_freq.c to all the stages
Change-Id: I3120a52e21cf4ad03bb1d16b5b2b8a5e68aabf3f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14339 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 328a5b43a7..3e307f5b86 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -25,6 +25,7 @@ romstage-y += gpio.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += memmap.c
romstage-y += mmap_boot.c
+romstage-y += tsc_freq.c
smm-y += placeholders.c
@@ -40,6 +41,7 @@ ramstage-y += mmap_boot.c
ramstage-y += uart.c
ramstage-y += northbridge.c
ramstage-y += spi.c
+ramstage-y += tsc_freq.c
postcar-y += exit_car.S
postcar-y += memmap.c