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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-26 08:53:59 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-06 20:42:52 +0100
commitd45114ff59284cebc0c03821cc4d7782ca3bacf8 (patch)
treee7e02fdd04b60ce9735840780ae4bb734c3845f1 /src/soc/intel
parentb1de92ee04c7a410cd50bd5d6e155d7343003fef (diff)
downloadcoreboot-d45114ff59284cebc0c03821cc4d7782ca3bacf8.tar.xz
intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/sch/smihandler.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/sch/smihandler.c b/src/soc/intel/sch/smihandler.c
index 57eb35c23b..6982f58e82 100644
--- a/src/soc/intel/sch/smihandler.c
+++ b/src/soc/intel/sch/smihandler.c
@@ -275,7 +275,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
u16 pm1_sts;
u32 smi_sts, gpe0_sts, tco_sts;
- pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
+ pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc;
printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
/* We need to clear the SMI status registers, or we won't see what's
@@ -325,7 +325,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
if (tco_sts & (1 << 8)) { // BIOSWR
u8 bios_cntl;
- bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+ bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
if (bios_cntl & 1) {
/* BWE is RW, so the SMI was caused by a
* write to BWE, not by a write to the BIOS
@@ -338,7 +338,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
* box.
*/
printk(BIOS_DEBUG, "Switching back to RO\n");
- pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
} /* No else for now? */
}
}