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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2019-02-15 11:55:20 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-02-28 09:26:01 +0000
commitdb9e9ac30d12ac4fa548c01b907193503a5ae421 (patch)
tree6c35b66ab58a5b9d0c40f436e7cdc1b1cd8d3872 /src/soc/intel
parentba8af5807c83244c947571caa7f3c488f4e581a1 (diff)
downloadcoreboot-db9e9ac30d12ac4fa548c01b907193503a5ae421.tar.xz
soc/intel/cannonlake: Add PCH series check for CML LP PCH
TEST=Verify PM_STS1 value is is not 0xFF. Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/31434 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/lpc.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c33b3c33d4..c06ce97053 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -70,19 +70,25 @@ void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
uint8_t get_pch_series(void)
{
uint16_t lpc_did_hi_byte;
-
+ uint8_t pch_series = PCH_UNKNOWN_SERIES;
/*
* Fetch upper 8 bits on LPC device ID to determine PCH type
* Adding 1 to the offset to fetch upper 8 bits
*/
lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
- if (lpc_did_hi_byte == 0x9D)
- return PCH_LP;
- else if (lpc_did_hi_byte == 0xA3)
- return PCH_H;
- else
- return PCH_UNKNOWN_SERIES;
+ switch (lpc_did_hi_byte) {
+ case 0x9D: /* CNL-LP */
+ case 0x02: /* CML-LP */
+ pch_series = PCH_LP;
+ break;
+ case 0xA3:
+ pch_series = PCH_H;
+ break;
+ default:
+ break;
+ }
+ return pch_series;
}
#if ENV_RAMSTAGE