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authorArthur Heymans <arthur@aheymans.xyz>2018-11-29 14:08:15 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 13:33:21 +0000
commitf6cfbf380488d74f5b420d90d02e59399b83fed9 (patch)
treeb784e6fd8901ebd4fcaced9f39b2e6090f7f8a70 /src/soc/intel
parent4ff7921753b098980210f73992c1519af6ff68b7 (diff)
downloadcoreboot-f6cfbf380488d74f5b420d90d02e59399b83fed9.tar.xz
soc/intel/baytrail: Use postcar_frame functions to set up frame
Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29929 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c83
1 files changed, 19 insertions, 64 deletions
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 18c9353d10..dd1fd29c7d 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -241,76 +241,31 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
return stack;
}
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void *setup_stack_and_mtrrs(void)
{
- int num_mtrrs;
- uint32_t *slot;
- uint32_t mtrr_mask_upper;
- uint32_t top_of_ram;
-
- /* Top of stack needs to be aligned to a 4-byte boundary. */
- slot = (void *)romstage_ram_stack_top();
- num_mtrrs = 0;
-
- /* The upper bits of the MTRR mask need to set according to the number
- * of physical address bits. */
- mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
-
- /* The order for each MTRR is value then base with upper 32-bits of
- * each value coming before the lower 32-bits. The reasoning for
- * this ordering is to create a stack layout like the following:
- * +0: Number of MTRRs
- * +4: MTRR base 0 31:0
- * +8: MTRR base 0 63:32
- * +12: MTRR mask 0 31:0
- * +16: MTRR mask 0 63:32
- * +20: MTRR base 1 31:0
- * +24: MTRR base 1 63:32
- * +28: MTRR mask 1 31:0
- * +32: MTRR mask 1 63:32
- */
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
- num_mtrrs++;
+ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. The top of RAM under 4GiB is the
- * start of the TSEG region. It is required to be 8MiB aligned. Set
- * this area as cacheable so it can be used later for ramstage before
- * setting up the entire RAM as cacheable. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /* Cache 8MiB at the top of ram. Top of RAM is where the TSEG
- * region resides. However, it is not restricted to SMM mode until
- * SMM has been relocated. By setting the region to cacheable it
- * provides faster access when relocating the SMM handler as well
- * as using the TSEG region for other purposes. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs. */
- slot = stack_push(slot, num_mtrrs);
-
- return slot;
+ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+ /* Cache at least 8 MiB below the top of ram, and at most 8 MiB
+ * above top of the ram. This satisfies MTRR alignment requirement
+ * with different TSEG size configurations.
+ */
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
+ MTRR_TYPE_WRBACK);
+
+ return postcar_commit_mtrrs(&pcf);
}