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authorAbhay kumar <abhay.kumar@intel.com>2017-09-20 15:17:42 -0700
committerAaron Durbin <adurbin@chromium.org>2017-09-27 04:01:45 +0000
commitfcf88205050aed4f26b1afc74f3fa5c39a0de2d8 (patch)
tree9b0ab6ea6c6fea3f724b5575f28f510569810adb /src/soc/intel
parent9cffe25ce0b06a19e3e18978ea83e006f64886a2 (diff)
downloadcoreboot-fcf88205050aed4f26b1afc74f3fa5c39a0de2d8.tar.xz
soc/intel/cannonlake: Add FSP GOP support
1. Add FSP GOP config. 2. Pass VBT to FSP. Change-Id: Icf836d683ae00cd034c853bc9ce965d4de5f7413 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/21628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/cannonlake/Kconfig2
-rw-r--r--src/soc/intel/cannonlake/chip.c17
2 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index fe80a20d67..03f98d23e5 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -18,10 +18,12 @@ config CPU_SPECIFIC_OPTIONS
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB
+ select HAVE_FSP_GOP
select HAVE_HARD_RESET
select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
select INTEL_CAR_NEM_ENHANCED
+ select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 6616b66b32..e1cf167629 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -20,10 +20,14 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <romstage_handoff.h>
+#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
+static void *vbt;
+static struct region_device vbt_rdev;
+
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
static const char *soc_acpi_name(const struct device *dev)
{
@@ -160,10 +164,17 @@ static void soc_enable(device_t dev)
dev->ops = &cpu_bus_ops;
}
+static void soc_final(void *data)
+{
+ if (vbt)
+ rdev_munmap(&vbt_rdev, vbt);
+}
+
struct chip_operations soc_intel_cannonlake_ops = {
CHIP_NAME("Intel Cannonlake")
.enable_dev = &soc_enable,
.init = &soc_init_pre_device,
+ .final = &soc_final
};
/* UPD parameters to be initialized before SiliconInit */
@@ -177,6 +188,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Parse device tree and enable/disable devices */
parse_devicetree(params);
+ /* Save VBT info and mapping */
+ vbt = vbt_get(&vbt_rdev);
+
+ /* Load VBT before devicetree-specific config. */
+ params->GraphicsConfigPtr = (uintptr_t)vbt;
+
/* Set USB OC pin to 0 first */
for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {
params->Usb2OverCurrentPin[i] = 0;