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| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-20 01:39:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:36 +0200 |
| commit | 074a028ef715763ecda99386d472c751092150a1 (patch) | |
| tree | 3901c0a1a18f31ecf520060449cb1edfee4d3d52 /src/soc/intel | |
| parent | f6d7baa8fa31a87e4a6f47fc3da82fc093f114a3 (diff) | |
| download | coreboot-074a028ef715763ecda99386d472c751092150a1.tar.xz | |
Samus: Synchronization with FRC to enable PCIe Relaxed Order.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 8455d95442ee9a39ecb182abf319469dde06d324
Original-BUG=None
Original-TEST=Modify settings, build and update the image to Samus and
Original-check the settings are applied to Registers.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I3d407b8f1cb4a6ea3d6879a8581156a73f98220f
Original-Reviewed-on: https://chromium-review.googlesource.com/219073
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ide6e747f1eccb74be2e21e76f592a919399bee31
Reviewed-on: http://review.coreboot.org/9206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index d7a3e82747..5efcb73a28 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -207,6 +207,9 @@ static const struct reg_script pch_misc_init_script[] = { /* Clear status bits to prevent unexpected wake */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x3310, 0x0000002f), REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x3f02, ~0x0000000f, 0), + /* Enable PCIe Releaxed Order */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2314, (1 << 31) | (1 << 7)), + REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x1114, (1 << 15) | (1 << 14)), /* Setup SERIRQ, enable continuous mode */ REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), #if !CONFIG_SERIRQ_CONTINUOUS_MODE |