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authorZhao, Lijian <lijian.zhao@intel.com>2016-04-22 11:19:44 -0700
committerAaron Durbin <adurbin@chromium.org>2016-04-28 05:14:47 +0200
commit2b9a5f5688db5a19a2511a19b91025440d9c138f (patch)
tree36494d93f9e13f218992a5b5fc9195cf082f59ce /src/soc/intel
parentcbf1a0fec8b84dc936a35428b835501ad0f46a30 (diff)
downloadcoreboot-2b9a5f5688db5a19a2511a19b91025440d9c138f.tar.xz
soc/intel/apollolake: Fix northbridge _crs scope
Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/acpi/northbridge.asl167
1 files changed, 84 insertions, 83 deletions
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 8415ffe8ad..a73a8a96bd 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -36,97 +36,98 @@ Device (MCHC)
Offset(0xBC),
TLUD, 32, /* Top of Low Useable DRAM */
}
- Name (MCRS, ResourceTemplate()
- {
- /* Bus Numbers */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
-
- /* IO Region 0 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
-
- /* PCI Config Space */
- Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
-
- /* IO Region 1 */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
-
- /* VGA memory (0xa0000-0xbffff) */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
- 0x00020000,,,)
-
- /* Data and GFX stolen memory */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- Cacheable, ReadWrite,
- 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
- 0x04200000,,, STOM)
-
- /*
- * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
- * This assumes that MMCONF is placed after PCI config space,
- * and that no resources are allocated after the MMCONF region.
- * This works, sicne MMCONF is hardcoded to 0xe00000000.
- */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x00000000, 0x00000000, 0x00000000,
- 0x00000000,,, PM01)
-
- /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
- QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000, 0x10000, 0x1ffff, 0x00000000,
- 0x10000,,, PM02)
- })
-
- /* Current Resource Settings */
- Method (_CRS, 0, Serialized)
- {
+}
+Name (MCRS, ResourceTemplate()
+{
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,,)
+
+ /* Data and GFX stolen memory */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000,
+ 0x04200000,,, STOM)
+
+ /*
+ * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
+ * This assumes that MMCONF is placed after PCI config space,
+ * and that no resources are allocated after the MMCONF region.
+ * This works, sicne MMCONF is hardcoded to 0xe00000000.
+ */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000,,, PM01)
+
+ /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000, 0x10000, 0x1ffff, 0x00000000,
+ 0x10000,,, PM02)
+})
+
+/* Current Resource Settings */
+Method (_CRS, 0, Serialized)
+{
- /* Find PCI resource area in MCRS */
- CreateDwordField (MCRS, ^PM01._MIN, PMIN)
- CreateDwordField (MCRS, ^PM01._MAX, PMAX)
- CreateDwordField (MCRS, ^PM01._LEN, PLEN)
+ /* Find PCI resource area in MCRS */
+ CreateDwordField (MCRS, ^PM01._MIN, PMIN)
+ CreateDwordField (MCRS, ^PM01._MAX, PMAX)
+ CreateDwordField (MCRS, ^PM01._LEN, PLEN)
- /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
- And(^TLUD, 0xFFF00000, PMIN)
- /* Read MMCONF base */
- And(^MCNF, 0xF0000000, PMAX)
+ /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
+ And(^MCHC.TLUD, 0xFFF00000, PMIN)
+ /* Read MMCONF base */
+ And(^MCHC.MCNF, 0xF0000000, PMAX)
- /* Calculate PCI MMIO Length */
- Add(Subtract(PMAX, PMIN), 1, PLEN)
+ /* Calculate PCI MMIO Length */
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
- /* Find GFX resource area in GCRS */
- CreateDwordField(MCRS, ^STOM._MIN, GMIN)
- CreateDwordField(MCRS, ^STOM._MAX, GMAX)
- CreateDwordField(MCRS, ^STOM._LEN, GLEN)
+ /* Find GFX resource area in GCRS */
+ CreateDwordField(MCRS, ^STOM._MIN, GMIN)
+ CreateDwordField(MCRS, ^STOM._MAX, GMAX)
+ CreateDwordField(MCRS, ^STOM._LEN, GLEN)
- /* Read BGSM */
- And(^BGSM, 0xFFF00000, GMIN)
+ /* Read BGSM */
+ And(^MCHC.BGSM, 0xFFF00000, GMIN)
- /* Read TOLUD */
- And(^TLUD, 0xFFF00000, GMAX)
- Decrement(GMAX)
- Add(Subtract(GMAX, GMIN), 1, GLEN)
+ /* Read TOLUD */
+ And(^MCHC.TLUD, 0xFFF00000, GMAX)
+ Decrement(GMAX)
+ Add(Subtract(GMAX, GMIN), 1, GLEN)
- /* Patch PM02 range based on Memory Size */
- CreateQwordField (MCRS, ^PM02._MIN, MMIN)
- CreateQwordField (MCRS, ^PM02._MAX, MMAX)
- CreateQwordField (MCRS, ^PM02._LEN, MLEN)
+ /* Patch PM02 range based on Memory Size */
+ CreateQwordField (MCRS, ^PM02._MIN, MMIN)
+ CreateQwordField (MCRS, ^PM02._MAX, MMAX)
+ CreateQwordField (MCRS, ^PM02._LEN, MLEN)
- Store (^TUUD, Local0)
+ Store (^MCHC.TUUD, Local0)
- If (LLessEqual (Local0, 0x1000000000))
- {
- Store (0, MMIN)
- Store (0, MLEN)
- }
- Subtract (Add (MMIN, MLEN), 1, MMAX)
-
- Return (MCRS)
+ If (LLessEqual (Local0, 0x1000000000))
+ {
+ Store (0, MMIN)
+ Store (0, MLEN)
}
+ Subtract (Add (MMIN, MLEN), 1, MMAX)
+
+ Return (MCRS)
}
+