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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-08 19:22:07 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-05-20 16:36:28 +0000
commit7d6bc60db9427f029f990002870e40541601a209 (patch)
tree40b34a1431710e1be32205c5a2711664ab628244 /src/soc/intel
parent32585de39ea15b4192e213b7cfcf46485bfd0d2f (diff)
downloadcoreboot-7d6bc60db9427f029f990002870e40541601a209.tar.xz
tigerlake: enable DPTF functionality for volteer
Enable DPTF functionality for volteer platform BRANCH=None BUG=b:149722146 TEST=Built and tested on volteer system Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/acpi/dptf.asl32
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c3
2 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/common/acpi/dptf.asl b/src/soc/intel/common/acpi/dptf.asl
new file mode 100644
index 0000000000..bd6d63ef40
--- /dev/null
+++ b/src/soc/intel/common/acpi/dptf.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define DPTF_CPU_DEVICE TCPU
+#define DPTF_CPU_ADDR 0x00040000
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE 80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0 90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1 80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2 70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3 60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4 50
+#endif
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index cf106cbe16..0c67105300 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -193,6 +193,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+ /* Enable TCPU for processor thermal control */
+ params->Device4Enable = config->Device4Enable;
+
/* LAN */
dev = pcidev_path_on_root(PCH_DEVFN_GBE);
if (!dev)