diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-25 21:34:42 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:46 +0200 |
| commit | 8ef55ee9969de3003eae9e3113b7497799ba14ec (patch) | |
| tree | 5b4103c250ddbaf1b15d636072d9b9a11f741c58 /src/soc/intel | |
| parent | 87d4a201aba0cb1c422546a42fdc7e9b10c61fdb (diff) | |
| download | coreboot-8ef55ee9969de3003eae9e3113b7497799ba14ec.tar.xz | |
Broadwell: Revise programming flow for write-once registers
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d2862b6c1ccc77845cb3e08688a72c0655ea79c9
Original-BUG=chrome-os-partner:31424.
Original-TEST=Build a image and check the programming value is correct on
Original-Samus.
Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Original-Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Original-Reviewed-on: https://chromium-review.googlesource.com/219985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3711aa0f1f918baebb4fd77a3615bdf5956ba844
Reviewed-on: http://review.coreboot.org/9209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index de23f3eb64..22eaab9c5d 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -547,16 +547,15 @@ static void pch_pcie_early(struct device *dev) pcie_update_cfg8(dev, 0xf5, 0x0f, 0); + /* Set Extended Capability to offset 200h and Advanced Error Report. */ + pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + if (rp == 1 || rp == 5 || rp == 6) pcie_update_cfg8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); - /* Set something involving advanced error reporting. */ - pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); - pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); - /* Read and write back write-once capability registers. */ pcie_update_cfg(dev, 0x34, ~0, 0); pcie_update_cfg(dev, 0x40, ~0, 0); |