diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-17 11:37:28 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-04-23 09:18:07 +0000 |
| commit | ae18f80febc3ecaacc0314e942a4f8b248bfcc4c (patch) | |
| tree | 0b18a060a00b7ec302e8bcb1fcb0edf166fbad5d /src/soc/intel | |
| parent | 7f5e73463882a92b64dc9f3ffd72a3bc0762300c (diff) | |
| download | coreboot-ae18f80febc3ecaacc0314e942a4f8b248bfcc4c.tar.xz | |
cpu/x86: move NXE and PAT accesses to paging module
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 20 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/msr.h | 10 |
3 files changed, 0 insertions, 35 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0b1599a804..e768f8c5a4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -314,23 +314,3 @@ void mca_configure(void) (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } - -void set_nxe(uint8_t enable) -{ - msr_t msr = rdmsr(IA32_EFER); - - if (enable) - msr.lo |= EFER_NXE; - else - msr.lo &= ~EFER_NXE; - - wrmsr(IA32_EFER, msr); -} - -void set_pat(uint64_t pat) -{ - msr_t msr; - msr.lo = pat; - msr.hi = pat >> 32; - wrmsr(MSR_IA32_PAT, msr); -} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 0c7f2c42d3..34caf4c252 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -159,9 +159,4 @@ uint32_t cpu_get_max_turbo_ratio(void); /* Configure Machine Check Architecture support */ void mca_configure(void); -/* Set/Clear NXE bit in IA32_EFER MSR */ -void set_nxe(uint8_t enable); - -/* Set PAT MSR */ -void set_pat(uint64_t pat); #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 5cfce17894..22e8862e98 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,7 +72,6 @@ #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc -#define MSR_IA32_PAT 0x277 #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 @@ -143,13 +142,4 @@ #define SGX_RESOURCE_MASK_LO (0xfffff000UL) #define SGX_RESOURCE_MASK_HI (0xfffffUL) -/* Intel SDM: Table 2-1 - * IA-32 architectural MSR: Extended Feature Enable Register - */ -#define IA32_EFER 0xC0000080 -#define EFER_NXE (1 << 11) -#define EFER_LMA (1 << 10) -#define EFER_LME (1 << 8) -#define EFER_SCE (1 << 0) - #endif /* SOC_INTEL_COMMON_MSR_H */ |