diff options
| author | Felix Singer <felixsinger@posteo.net> | 2020-07-29 23:20:52 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-08-08 16:32:41 +0000 |
| commit | e21866781f73dfa468ce5da3db7e86b39e2bb4d8 (patch) | |
| tree | ca9d46e122f902965f9f168df6db8d7b5b838f06 /src/soc/intel | |
| parent | 4d5c4e069cb99e715d04bf238e406a008f16707d (diff) | |
| download | coreboot-e21866781f73dfa468ce5da3db7e86b39e2bb4d8.tar.xz | |
soc/intel/skylake: Enable CIO depending on devicetree configuration
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.
Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 80e89f6cce..9239fd24de 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -229,7 +229,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) memcpy(params->SerialIoDevMode, config->SerialIoDevMode, sizeof(params->SerialIoDevMode)); - params->PchCio2Enable = config->Cio2Enable; + dev = pcidev_path_on_root(PCH_DEVFN_CIO); + params->PchCio2Enable = dev && dev->enabled; dev = pcidev_path_on_root(SA_DEVFN_IMGU); params->SaImguEnable = dev && dev->enabled; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 33fe52c2b6..b1cf4dcb9b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -300,9 +300,6 @@ struct soc_intel_skylake_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage i2c_voltage[CONFIG_SOC_INTEL_I2C_DEV_MAX]; - /* Camera */ - u8 Cio2Enable; - /* eMMC and SD */ u8 ScsEmmcHs400Enabled; u8 EmmcHs400DllNeed; |