diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-10-09 08:50:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 06:15:06 +0000 |
| commit | edac4ef6d4c25414bc0e6200875d57fff9e3346e (patch) | |
| tree | 2c2477267280bc7e0d90331c57b5dea484a14c1d /src/soc/intel | |
| parent | 23e88135bb86361cbd4c260a1a38bb7fda2b2338 (diff) | |
| download | coreboot-edac4ef6d4c25414bc0e6200875d57fff9e3346e.tar.xz | |
mb, soc/intel: Reorganize CNVi device entries in devicetree
This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/chipset.cb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index 1daa64bb3d..54f7924b37 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -112,9 +112,7 @@ chip soc/intel/tigerlake end device pci 14.1 alias south_xdci off end device pci 14.2 alias shared_ram off end - chip drivers/wifi/generic - device pci 14.3 alias cnvi_wifi off end - end + device pci 14.3 alias cnvi_wifi off end device pci 15.0 alias i2c0 off end device pci 15.1 alias i2c1 off end device pci 15.2 alias i2c2 off end |