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authorAndrey Petrov <andrey.petrov@intel.com>2016-02-25 18:39:38 -0800
committerMartin Roth <martinroth@google.com>2016-03-08 13:51:45 +0100
commit0d187917554f710ac3af04c59bd18b59837a178c (patch)
treeb2dc9a19702724de112f636100a00df2d5b7477e /src/soc/intel
parentb4831460a5e61e5069021c20d7baf29fde485570 (diff)
downloadcoreboot-0d187917554f710ac3af04c59bd18b59837a178c.tar.xz
soc/intel/apollolake: Enable using FSP 2.0 driver
Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13806 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/apollolake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e113369917..022c2e4b30 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE
select UDELAY_TSC
select TSC_CONSTANT_RATE
+ select PLATFORM_USES_FSP2_0
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"