soc/intel/common: Fix typos

Fix typos and replace spaces with tab in macro definitions.

TEST=Build and Boot hatch board

Change-Id: I43b2df7defc97aaeb7c8c9dfbe08ce78ba81f39b
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38384
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 14 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index bf829b0fe1..515f1a47d5 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -20,26 +20,26 @@
 #include <stdint.h>
 
 /* MKHI Command groups */
-#define MKHI_GROUP_ID_CBM       0x0
-#define MKHI_GROUP_ID_HMRFPO    0x5
+#define MKHI_GROUP_ID_CBM	0x0
+#define MKHI_GROUP_ID_HMRFPO	0x5
 
 /* Global Reset Command ID */
-#define MKHI_CBM_GLOBAL_RESET_REQ   0xb
+#define MKHI_CBM_GLOBAL_RESET_REQ	0xb
 
 /* Origin of Global Reset command */
-#define GR_ORIGIN_BIOS_POST     0x2
+#define GR_ORIGIN_BIOS_POST	0x2
 
 /* HMRFPO Command Ids */
-#define MKHI_HMRFPO_ENABLE      0x1
-#define MKHI_HMRFPO_GET_STATUS  0x3
+#define MKHI_HMRFPO_ENABLE	0x1
+#define MKHI_HMRFPO_GET_STATUS	0x3
 
 /* ME Current Working States */
-#define ME_HFS1_CWS_NORMAL      0x5
+#define ME_HFS1_CWS_NORMAL	0x5
 
 /* ME Current Operation Modes */
-#define ME_HFS1_COM_NORMAL      0x0
-#define ME_HFS1_COM_SOFT_TEMP_DISABLE   0x3
-#define ME_HFS1_COM_SECOVER_MEI_MSG     0x5
+#define ME_HFS1_COM_NORMAL	0x0
+#define ME_HFS1_COM_SOFT_TEMP_DISABLE	0x3
+#define ME_HFS1_COM_SECOVER_MEI_MSG	0x5
 
 /* HFSTS register offsets in PCI config space */
 enum {
@@ -106,14 +106,14 @@ heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t cse_addr);
 /*
  * Sends snd_msg of size snd_sz, and reads message into buffer pointed by
  * rcv_msg of size rcv_sz
- * Returns 0 on failure a 1 on success.
+ * Returns 0 on failure and 1 on success.
  */
 int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz);
 
 /*
  * Attempt device reset. This is useful and perhaps only thing left to do when
  * CPU and CSE are out of sync or CSE fails to respond.
- * Returns 0 on failure a 1 on success.
+ * Returns 0 on failure and 1 on success.
  */
 int heci_reset(void);
 
@@ -132,14 +132,14 @@ void set_host_ready(void);
 
 /*
  * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds.
- * Returns 0 on failure a 1 on success.
+ * Returns 0 on failure and 1 on success.
  */
 uint8_t wait_cse_sec_override_mode(void);
 
 /*
  * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be
  * GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY.
- * Returns -1 on failure a 0 on success.
+ * Returns -1 on failure and 0 on success.
  */
 int send_heci_reset_req_message(uint8_t rst_type);