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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-08 19:21:32 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-20 17:13:57 +0000 |
| commit | 21573e9f4e6c5ec1c5ab7da265f42642f832394b (patch) | |
| tree | d0d7b3d22cd2d551af87703ec0cd9f3373132e97 /src/soc/intel | |
| parent | afd03d8a28df60a058e73e4f1f4e0e89f8373bd1 (diff) | |
| download | coreboot-21573e9f4e6c5ec1c5ab7da265f42642f832394b.tar.xz | |
soc/intel/cannonlake: Add ACPI workaround for EMMC
Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.
BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.
Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 11564ae7d4..ed695fd580 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -14,6 +14,26 @@ */ Scope (\_SB.PCI0) { + /* EMMC */ + Device(PEMC) { + Name(_ADR, 0x001A0000) + + OperationRegion(SCSR, PCI_Config, 0x00, 0x100) + Field(SCSR, WordAcc, NoLock, Preserve) { + Offset(0xA2), // 0xA2, Device PG config + , 2, + PGEN, 1 // [BIT2] PGE - PG Enable + } + + Method(_PS0, 0, Serialized) { + Stall (50) // Sleep 50 ms + Store(0, PGEN) // Disable PG + } + + Method(_PS3, 0, Serialized) { + Store(1, PGEN) // Enable PG + } + } /* SD CARD */ Device (SDXC) |