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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-20 13:34:56 +0000 |
| commit | 35e76dde7708d0646c56eaf3b5c063b27d2add62 (patch) | |
| tree | 6ad9d075128f38187b3683c4951ff0a3911f3ebe /src/soc/intel | |
| parent | efe3cfb476b39da5ece2583000e0f24b5daf560b (diff) | |
| download | coreboot-35e76dde7708d0646c56eaf3b5c063b27d2add62.tar.xz | |
soc/intel/skylake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/pmutil.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 329cea9621..eb36e48ace 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -173,6 +173,16 @@ uintptr_t soc_read_pmc_base(void) return (uintptr_t) (pmc_mmio_regs()); } +uint32_t *soc_pmc_etr_addr(void) +{ + /* + * The pointer returned must not be cached, because the address depends on the + * MMCONF base address and the assigned PCI bus number, which both may change + * during the boot process! + */ + return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; |