diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-01 08:47:51 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:06:53 +0000 |
| commit | 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch) | |
| tree | 8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/soc/intel | |
| parent | 603963e1ba4147ef31a72b94304708ab416e3b6a (diff) | |
| download | coreboot-419bfbc1f1e7bb40c1e5698e1f50d4e275665d97.tar.xz | |
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.
Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
29 files changed, 49 insertions, 120 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index e74599694d..bf5beacbb1 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -54,7 +54,7 @@ static const struct reg_script core_msr_script[] = { REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable support for MONITOR and MWAIT instructions */ - REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), + REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0), #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index b332478734..e39758c64b 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -16,7 +16,6 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 @@ -24,8 +23,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 486f5a39d2..e9925a24f5 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -108,7 +108,7 @@ static void fill_in_pattrs(void) stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index dcb62960f9..9969d5d4b6 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -17,6 +17,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/msr.h> #include "fmap_config.h" @@ -35,7 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 /* Save the BIST result. */ movl %eax, %ebp @@ -64,7 +64,7 @@ wait_for_sipi: post_code(0x22) /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx + movl $IA32_MCG_CAP, %ecx rdmsr movzx %al, %ebx /* First variable MTRR. */ diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 66fde22d99..f9c3014273 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -60,9 +60,9 @@ void set_max_freq(void) msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ void set_max_freq(void) perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 6ed12afa5f..27903e86e0 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -175,7 +175,7 @@ static void per_cpu_smm_trigger(void) msr_t msr_value; /* Need to make sure that all cores have microcode loaded. */ - msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + msr_value = rdmsr(IA32_BIOS_SIGN_ID); if (msr_value.hi == 0) intel_microcode_load_unlocked(pattrs->microcode_patch); diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 1a79b2faf5..6137820e9f 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -17,8 +17,6 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 @@ -26,8 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 20c09d5d52..a12db8034d 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -112,7 +112,7 @@ static void fill_in_pattrs(void) stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007c66..72dbca5af9 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ void set_max_freq(void) msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of @@ -91,7 +91,7 @@ void set_max_freq(void) perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 3ef0d722b6..2f9f78f69e 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -546,10 +546,10 @@ static void set_energy_perf_bias(u8 policy) return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } @@ -557,11 +557,10 @@ static void set_energy_perf_bias(u8 policy) static void configure_mca(void) { msr_t msr; - const unsigned int mcg_cap_msr = 0x179; int i; int num_banks; - msr = rdmsr(mcg_cap_msr); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index c2a939e392..f791bdd924 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,9 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 @@ -32,26 +29,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRRphysBase_MSR 0x1f4 #define EMRRphysMask_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_EMRRphysBase_MSR 0x2f4 #define UNCORE_EMRRphysMask_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ba87045555..1fdaf69241 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -18,6 +18,7 @@ #include <chip.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> @@ -126,10 +127,10 @@ static void set_energy_perf_bias(u8 policy) return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); } static void configure_c_states(void) diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index c63c921827..e3bd5f6ebc 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,13 +20,6 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_VR_MISC_CONFIG2 0x636 #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 684f82786a..17b8dc063c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -17,6 +17,7 @@ #include <commonlib/helpers.h> #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> #include <rules.h> @@ -306,7 +307,7 @@ car_cqos: wrmsr /* Set CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ wrmsr @@ -339,7 +340,7 @@ car_cqos: post_code(0x27) /* Cache is populated. Use mask 1 that will block evicts */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ or $1, %edx /* select mask 1 */ @@ -410,7 +411,7 @@ find_llc_subleaf: */ shl %cl, %eax subl $0x02, %eax - movl $MSR_IA32_L3_MASK_1, %ecx + movl $IA32_L3_MASK_1, %ecx xorl %edx, %edx wrmsr /* @@ -419,12 +420,12 @@ find_llc_subleaf: * For SKL SOC, data size remains 256K consistently. * Hence, creating 1-way associative cache for Data */ - mov $MSR_IA32_L3_MASK_2, %ecx + mov $IA32_L3_MASK_2, %ecx mov $0x01, %eax xorl %edx, %edx wrmsr /* - * Set MSR_IA32_PQR_ASSOC = 0x02 + * Set IA32_PQR_ASSOC = 0x02 * * Possible values: * 0: Default value, no way mask should be applied @@ -432,7 +433,7 @@ find_llc_subleaf: * 2: Apply way mask 2 to LLC * 3: Shouldn't be use in NEM Mode */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x02, %eax xorl %edx, %edx wrmsr @@ -444,11 +445,11 @@ find_llc_subleaf: cld rep stosl /* - * Set MSR_IA32_PQR_ASSOC = 0x01 + * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. * i.e. way 0 is protected from eviction. */ - movl $MSR_IA32_PQR_ASSOC, %ecx + movl $IA32_PQR_ASSOC, %ecx movl $0x01, %eax xorl %edx, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 86feddca43..a4d16e8022 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/x86/cr.h> #include <intelblocks/msr.h> @@ -80,7 +81,7 @@ car_cqos_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr @@ -101,7 +102,7 @@ car_nem_enhanced_teardown: wrmsr /* Reset CLOS selector to 0 */ - mov $MSR_IA32_PQR_ASSOC, %ecx + mov $IA32_PQR_ASSOC, %ecx rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a0496a0..ebbdabd3e8 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ void cpu_set_p_state_to_turbo_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ void cpu_set_p_state_to_nominal_tdp_ratio(void) perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ void cpu_set_p_state_to_max_non_turbo_ratio(void) perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 154f03b81e..63b92013a3 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,16 +39,13 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +/* This is burst mode BIT 38 in IA32_MISC_ENABLE MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 @@ -76,8 +66,6 @@ #define MSR_EVICT_CTL 0x2e0 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) #define MSR_PKG_POWER_SKU_UNIT 0x606 @@ -122,11 +110,6 @@ #define SMBASE_MSR 0xc20 #define IEDBASE_MSR 0xc22 -#define MSR_IA32_PQR_ASSOC 0x0c8f -/* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) -#define MSR_IA32_L3_MASK_1 0x0c91 -#define MSR_IA32_L3_MASK_2 0x0c92 #define MSR_L2_QOS_MASK(reg) (0xd10 + reg) /* MTRR_CAP_MSR bits */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index daedcfcf5d..6050dec093 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -137,7 +137,7 @@ static void enable_sgx(void) msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */ wrmsr(IA32_FEATURE_CONTROL, msr); } diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c index 591ffbc6df..2cffdabd2e 100644 --- a/src/soc/intel/common/block/vmx/vmx.c +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -58,7 +58,7 @@ void vmx_configure(void *unused) msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { /* Enable VMX */ msr.lo |= FEATURE_ENABLE_VMX; wrmsr(IA32_FEATURE_CONTROL, msr); @@ -68,5 +68,5 @@ void vmx_configure(void *unused) msr = rdmsr(IA32_FEATURE_CONTROL); printk(BIOS_DEBUG, "VMX status: %s, %s\n", (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked"); + (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); } diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b7b5550aaa..676fab7cbd 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -44,9 +44,9 @@ static void denverton_core_init(struct device *cpu) /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index a2a42f178e..c2c6c4d2f8 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -18,12 +18,8 @@ #ifndef _DENVERTON_NS_MSR_H_ #define _DENVERTON_NS_MSR_H_ -#define MSR_PLATFORM_ID 0x17 #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 @@ -35,26 +31,16 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define EMRR_PHYS_BASE_MSR 0x1f4 #define EMRR_PHYS_MASK_MSR 0x1f5 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 #define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 #define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 -#define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index 4435256be8..b8fe7fe7ce 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -16,13 +16,10 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index fc50e649bf..f4cdaa8300 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -107,7 +107,7 @@ static void fill_in_pattrs(void) stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 1e32262999..4c91b0aed6 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -74,7 +74,7 @@ void report_platform_info(void) "Bay Trail-D (Desktop)", "Bay Trail-M (Mobile)", }; - msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID); + msr_t platform_id = rdmsr(IA32_PLATFORM_ID); uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 66fde22d99..f9c3014273 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -60,9 +60,9 @@ void set_max_freq(void) msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ @@ -74,7 +74,7 @@ void set_max_freq(void) perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index ffa33da4b2..ed42fdf4cf 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -18,14 +18,9 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce -#define IA32_MCG_CAP 0x179 -#define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad -#define IA32_MC0_CTL 0x400 -#define IA32_MC0_STATUS 0x401 #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 #define MSR_CONFIG_TDP_NOMINAL 0x648 diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 7165080b68..7b94268a02 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -76,7 +76,7 @@ static void fill_in_pattrs(void) printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 7a66ed0e33..cf039d5845 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -357,10 +357,10 @@ static void set_energy_perf_bias(u8 policy) return; /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr = rdmsr(IA32_ENERGY_PERF_BIAS); msr.lo &= ~0xf; msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); + wrmsr(IA32_ENERGY_PERF_BIAS, msr); printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 780f94fdc9..6da9325d87 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,13 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_THERM_INTERRUPT 0x19b -#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 -#define ENERGY_POLICY_PERFORMANCE 0 -#define ENERGY_POLICY_NORMAL 6 -#define ENERGY_POLICY_POWERSAVE 15 -#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 |