diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-06-03 13:59:28 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-06-10 03:42:38 +0200 |
| commit | 47d4f7cec3bd6a4fb632db5901fff4676e562114 (patch) | |
| tree | dadbb7724a139265210de42865383d6ea52d2d87 /src/soc/intel | |
| parent | c9bf8bfabfeb75500ea0f3b4a0bfb5ce5485ae23 (diff) | |
| download | coreboot-47d4f7cec3bd6a4fb632db5901fff4676e562114.tar.xz | |
soc/intel/apollolake: FSP Header file update for FSP 139_40
FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs
with the 139_40 release. In order to successfully pass through
memory/silicon init the header files must be updated to the latest
versions
BUG=chrome-os-partner:52784
BRANCH=none
TEST=built and booted
Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15066
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspUpd.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 14 |
3 files changed, 18 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h index 61d03a2901..4d865f5e8d 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspUpd.h @@ -33,10 +33,10 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPD_H__ #define __FSPUPD_H__ -#define FSPT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */ #endif diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index 906f6a4bb6..5f5f367b45 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -526,7 +526,11 @@ struct FSP_M_CONFIG { /** Offset 0x0131 **/ - uint8_t ReservedFspmUpd[31]; + void* MrcBootDataPtr; + +/** Offset 0x0135 +**/ + uint8_t ReservedFspmUpd[27]; } __attribute__((packed)); /** Fsp M Test Configuration diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index 92c2d752bc..d4ecd369cb 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -167,10 +167,10 @@ struct FSP_S_CONFIG { uint32_t HdaVerbTablePtr; /** Offset 0x0039 - Enable/Disable P2SB device hidden. - Enable/Disable P2SB device hidden. 0:Disable, 1:Enable(Default). + Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable. $EN_DIS **/ - uint8_t HideP2sb; + uint8_t P2sbUnhide; /** Offset 0x003A - IPU Enable/Disable Enable/Disable IPU Device. 0:Disable, 1:Enable(Default). @@ -1477,9 +1477,15 @@ struct FSP_S_CONFIG { **/ uint8_t PcieRpSelectableDeemphasis[6]; -/** Offset 0x0326 +/** Offset 0x0326 - Os Selection Mode + Select OS mode. 0:Windows(default), 1:Android, 2:Win7 + $EN_DIS +**/ + uint8_t OsSelection; + +/** Offset 0x0327 **/ - uint8_t ReservedFspsUpd[10]; + uint8_t ReservedFspsUpd[9]; } __attribute__((packed)); /** Fsp S Test Configuration |