diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-09-19 14:55:24 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-21 10:59:40 +0200 |
| commit | 6fcfd919f1f6231bb03eefcff01cc39cb18abb90 (patch) | |
| tree | ba51ccef4fadab7d518a8ec97e7be44bacc4a729 /src/soc/intel | |
| parent | 401bd31b2d9efed119d82eb4c153bd273fe64b49 (diff) | |
| download | coreboot-6fcfd919f1f6231bb03eefcff01cc39cb18abb90.tar.xz | |
soc/apollolake: Correct the comment section in gpio.asl
This patch corrects the comment section in gpio.asl for
GPE method.
Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16647
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/gpio.asl | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 4f3bc3ee2c..ffc5b75937 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -191,7 +191,8 @@ scope (\_SB) { Scope(\_GPE) { - /* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads + /* + * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI * GPE0a_EN at 0x430 is reserved. |