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| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-01-15 19:06:09 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 13:03:13 +0000 |
| commit | 82b8c3d1b025af5076f769d7754b7e1ae6bf5950 (patch) | |
| tree | e7f8676b312345f6a707a8f41aed23bc1cc04fdf /src/soc/intel | |
| parent | d1215269a7bc9b3df82548a7ebdb0e468b18e1df (diff) | |
| download | coreboot-82b8c3d1b025af5076f769d7754b7e1ae6bf5950.tar.xz | |
soc/intel/icelake: Fix AG3E programming in PMC
According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped
register but not pci configuration spaces, hence change the programming
method in icelake pmc driver.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7
Reviewed-on: https://review.coreboot.org/c/30947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/icelake/pmc.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 754aa5055d..9d1c47f63d 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -31,8 +31,9 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); - reg8 = pci_read_config8(dev, GEN_PMCON_B); + reg8 = read8(pmcbase + GEN_PMCON_A); switch (s5pwr) { case MAINBOARD_POWER_STATE_OFF: @@ -46,7 +47,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) break; } - pci_write_config8(dev, GEN_PMCON_B, reg8); + write8(pmcbase + GEN_PMCON_A, reg8); } /* |