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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-01-11 09:18:20 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-01-14 09:14:01 +0000 |
| commit | aa6d38859768486d3353edd7aef092b6318ac1bf (patch) | |
| tree | fd68b65d88d27ac89e5f8e5983b3e475197e1821 /src/soc/intel | |
| parent | 95c021b63a028e94a2f171b7e11774e2910898f9 (diff) | |
| download | coreboot-aa6d38859768486d3353edd7aef092b6318ac1bf.tar.xz | |
soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()
Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.
Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 003ae2270c..8ddca26be5 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -68,14 +68,16 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_EN, 0x340f); } - console_init(); - init_rtc(); - setup_gpio_io_address(); /* Call into mainboard. */ post_code(0x41); early_mainboard_romstage_entry(); + post_code(0x42); + console_init(); + init_rtc(); + setup_gpio_io_address(); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB |