diff options
| author | Julius Werner <jwerner@chromium.org> | 2017-03-17 14:14:14 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-03-28 22:16:24 +0200 |
| commit | b04cc6b90204d55096a56d4f3cd707148a634c97 (patch) | |
| tree | 6cdbeda0c7761435592692d987433c2cafeaa68b /src/soc/intel | |
| parent | 320edbe2ba01a1b5d9de25bc217b8dae936b8b17 (diff) | |
| download | coreboot-b04cc6b90204d55096a56d4f3cd707148a634c97.tar.xz | |
chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific
This callback was only required for a single mainboard, and it can
easily be moved to mainboard-specific code. This patch removes it from
the global namespace and isolates it to the Jecht board. (This makes
it easier to separate vboot and chromeos code in a later patch.)
Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index bd63e005f3..af95530c77 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/early_variables.h> +#include <bootmode.h> #include <console/console.h> #include <cbfs.h> #include <cbmem.h> @@ -35,7 +36,6 @@ #include <soc/reset.h> #include <soc/romstage.h> #include <soc/spi.h> -#include <vendorcode/google/chromeos/chromeos.h> /* Entry from cache-as-ram.inc. */ asmlinkage void *romstage_main(unsigned long bist, @@ -79,10 +79,6 @@ asmlinkage void *romstage_main(unsigned long bist, /* Call into mainboard. */ mainboard_romstage_entry(&rp); -#if CONFIG_CHROMEOS - save_chromeos_gpios(); -#endif - return setup_stack_and_mttrs(); } |