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authorSubrata Banik <subrata.banik@intel.com>2017-08-10 13:54:39 +0530
committerAaron Durbin <adurbin@chromium.org>2017-08-14 17:57:55 +0000
commitcdea598e8912e0320bd7337c1b6736025676b429 (patch)
treeb0718cf5523479cf6d11e36ad7d224396dbbcc91 /src/soc/intel
parentdfeb1c4da9be7ac97bd31f580ff2fff0c4b3256e (diff)
downloadcoreboot-cdea598e8912e0320bd7337c1b6736025676b429.tar.xz
common/block/lpss: Add CLK read function into LPSS common
This patch add new API to read LPSS CLK register. Also combine multiple LPSS_CLOCK_CTL_REG writes into a single write inside lpss_clk_update function. Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpss.h3
-rw-r--r--src/soc/intel/common/block/lpss/lpss.c13
2 files changed, 14 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index 138340df86..c6caae2675 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -30,4 +30,7 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
/* Check if controller is in reset. */
bool lpss_is_controller_in_reset(uintptr_t base);
+/* Read LPSS CLK register */
+uint32_t lpss_clk_read(uintptr_t base);
+
#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c
index feacef370f..6d4fb336f3 100644
--- a/src/soc/intel/common/block/lpss/lpss.c
+++ b/src/soc/intel/common/block/lpss/lpss.c
@@ -65,7 +65,16 @@ void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val)
addr += LPSS_CLOCK_CTL_REG;
clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val);
+ clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
- write32(addr, clk_sel | LPSS_CNT_CLK_UPDATE);
- write32(addr, clk_sel | LPSS_CNT_CLOCK_EN);
+ write32(addr, clk_sel);
+}
+
+uint32_t lpss_clk_read(uintptr_t base)
+{
+ uint8_t *addr = (void *)base;
+
+ addr += LPSS_CLOCK_CTL_REG;
+
+ return read32(addr);
}