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| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-04-22 09:41:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 16:06:39 +0000 |
| commit | d694f6e21b4a24c70adb55b65f095bc87a9878cd (patch) | |
| tree | 2236a1d63b8c16a039f33f67fed9ad7081759573 /src/soc/intel | |
| parent | f5b9369720ac0458be13e723468e27ab987b439e (diff) | |
| download | coreboot-d694f6e21b4a24c70adb55b65f095bc87a9878cd.tar.xz | |
mb/google/sarien: Add SMBIOS type 9 fields
Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 40d9f71eed..b17df4b21b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,7 @@ #include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> +#include <smbios.h> #include <stdint.h> #include <soc/gpio.h> #include <soc/pch.h> |