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| author | Furquan Shaikh <furquan@chromium.org> | 2017-02-20 13:33:32 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-02-22 00:40:32 +0100 |
| commit | f4b20af9d716ff57d78d5d576e2990903bd70842 (patch) | |
| tree | 69603260f4c95fbbcab75a6333e23068fda2dc18 /src/soc/intel | |
| parent | 39bfc6cb136e641955ca5db477be43715ac72454 (diff) | |
| download | coreboot-f4b20af9d716ff57d78d5d576e2990903bd70842.tar.xz | |
drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load
Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions