diff options
| author | pchandri <preetham.chandrian@intel.com> | 2016-01-11 15:22:45 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-22 12:59:59 +0100 |
| commit | f9495eae2c9a0894fb7a8917779880830b27a224 (patch) | |
| tree | b15fcce34cbafe31013fdf2306ca4c059a383d14 /src/soc/intel | |
| parent | 2cd9c05dc10462c105d889cecc148b5d87ac53fb (diff) | |
| download | coreboot-f9495eae2c9a0894fb7a8917779880830b27a224.tar.xz | |
intel/skylake: Thermal Design Power PL1 and PL2 Config Changes
Override the default PL2 values with one recommended by
Intel. Disable PL1 configuration via MMIO register.
BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
Change-Id: I10742f91cc7179de1482d42392338976e8082afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf
Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321392
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 14 |
2 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a46222d371..0390edaaea 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -323,6 +323,8 @@ struct soc_intel_skylake_config { * Setting to 0 (default) disables Heci1 and hides the device from OS */ u8 HeciEnabled; + /* PL2 Override value in Watts */ + u32 tdp_pl2_override; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 368738057f..2fa858257d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -116,8 +116,10 @@ void set_power_limits(u8 power_limit_1_time) msr_t msr = rdmsr(MSR_PLATFORM_INFO); msr_t limit; unsigned power_unit; - unsigned tdp, min_power, max_power, max_time; + unsigned tdp, min_power, max_power, max_time, tdp_pl2; u8 power_limit_1_val; + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = 28; @@ -127,7 +129,7 @@ void set_power_limits(u8 power_limit_1_time) /* Get units */ msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); + power_unit = 1 << (msr.lo & 0xf); /* Get power defaults for this SKU */ msr = rdmsr(MSR_PKG_POWER_SKU); @@ -162,15 +164,17 @@ void set_power_limits(u8 power_limit_1_time) /* Set short term power limit to 1.25 * TDP */ limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + tdp_pl2 = (conf->tdp_pl2_override == 0) ? + (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; /* Power limit 2 time is only programmable on server SKU */ wrmsr(MSR_PKG_POWER_LIMIT, limit); - /* Set power limit values in MCHBAR as well */ - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo; + /* Set PL2 power limit values in MCHBAR and disable PL1 */ + MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; /* Set DDR RAPL power limit by copying from MMIO to MSR */ |