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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-26 11:15:42 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-23 16:41:56 +0200 |
| commit | 0be6d939596249c6a0d6790648cadd7812ffe427 (patch) | |
| tree | 68ca2faf0ac86771821a7277772f91d81b7aa57e /src/soc/intel | |
| parent | caa5149b1ef4a77e9ce9abf65bbfcd54232ea129 (diff) | |
| download | coreboot-0be6d939596249c6a0d6790648cadd7812ffe427.tar.xz | |
intel/common: Add SMBIOS memory width
Add SMBIOS symbols to define the memory width. Update the Intel common
code to display the memory width and provide the memory width to SMBIOS.
Also display the memory frequency, size and bus width in decimal.
BRANCH=none
BUG=None
TEST=None
Change-Id: I67b814d79fdbbf6ce65ac6b4a8282ab15fb91369
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e59c7260afd180f3adcbeda7cef1b9eca3ed846
Original-Change-Id: Ibd26812c2aad4deaab62111b1e018be69c4faa7b
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/282115
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/romstage.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 370d973cf7..99ac890d5f 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -34,6 +34,7 @@ #include <memory_info.h> #include <reset.h> #include <romstage_handoff.h> +#include <smbios.h> #include <soc/intel/common/mrc_cache.h> #include <soc/intel/common/util.h> #include <soc/pei_wrapper.h> @@ -273,8 +274,10 @@ __attribute__((weak)) void mainboard_save_dimm_info( memory_info_hob->Revision); printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", memory_info_hob->MemoryType); - printk(BIOS_DEBUG, " 0x%04x: MemoryFrequencyInMHz\n", + printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", memory_info_hob->MemoryFrequencyInMHz); + printk(BIOS_DEBUG, " %d: DataWidth in bits\n", + memory_info_hob->DataWidth); printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", memory_info_hob->ErrorCorrectionType); printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", @@ -293,7 +296,7 @@ __attribute__((weak)) void mainboard_save_dimm_info( printk(BIOS_DEBUG, " DIMM %d\n", dimm); printk(BIOS_DEBUG, " 0x%02x: DimmId\n", dimm_info->DimmId); - printk(BIOS_DEBUG, " 0x%02x: SizeInMb\n", + printk(BIOS_DEBUG, " %d: SizeInMb\n", dimm_info->SizeInMb); } } @@ -333,6 +336,33 @@ __attribute__((weak)) void mainboard_save_dimm_info( channel_info->ChannelId; mem_info->dimm[index].dimm_num = dimm_info->DimmId; + switch (memory_info_hob->DataWidth) { + default: + case 8: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_8; + break; + + case 16: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_16; + break; + + case 32: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_32; + break; + + case 64: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_64; + break; + + case 128: + mem_info->dimm[index].bus_width = + MEMORY_BUS_WIDTH_128; + break; + } index++; } } |