diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-12-04 02:22:28 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-14 18:42:12 +0000 |
| commit | 1a2b70284895a9daef667aada307405039dc8cce (patch) | |
| tree | 0bca23d18f0d45e664a5e8967714183c7153ace9 /src/soc/intel | |
| parent | 4c2890d47ef03e5c638a9ac81d14cf3755f64cfc (diff) | |
| download | coreboot-1a2b70284895a9daef667aada307405039dc8cce.tar.xz | |
soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cse.h | 2 |
3 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index d2f94a41a9..30eb78e091 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c +romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1d261eaf36..036a50a4bf 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -775,7 +775,7 @@ static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info) return 0; } -void cse_fw_sync(void *unused) +void cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; @@ -814,5 +814,3 @@ void cse_fw_sync(void *unused) cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } } - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 64ee0ddd06..1a95e2efcb 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -236,7 +236,7 @@ uint8_t cse_wait_com_soft_temp_disable(void); * In software triggered recovery mode, the function allows CSE to boot from whatever is * currently selected partition. */ -void cse_fw_sync(void *unused); +void cse_fw_sync(void); /* Perform a board-specific reset sequence for CSE RO<->RW jump */ void cse_board_reset(void); |