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| author | xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> | 2020-08-31 17:05:48 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-09-02 00:43:22 +0000 |
| commit | 1d418281e098159339e292c1a4f0dde4bf35122c (patch) | |
| tree | cb518a20f3a6af8620ddbb08ff8916849b791dbb /src/soc/intel | |
| parent | 43092765e4cc26a4d5d8d746dfea27d0ec9f27cb (diff) | |
| download | coreboot-1d418281e098159339e292c1a4f0dde4bf35122c.tar.xz | |
mb/google/kukui: Add LPDDR4X support for fennel/cerise/stern
Modify the BOARD_SDRAM_TABLE_OFFSET as 0x10
BUG=b:162891673
BRANCH=kukui
TEST=make
Change-Id: I5a4794d6e899e35686c40a553b991643f9e35ea3
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianbo Zhang <zhangjianbo@huaqin.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions