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| author | Xiang Wang <wxjstz@126.com> | 2018-08-15 16:27:05 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-05 09:04:01 +0000 |
| commit | 22e0c560bb565642d52e4e0f8bab000c8d06f0b8 (patch) | |
| tree | a960e9bc01d3d4d9ddb65ba828b64d39a64baade /src/soc/intel | |
| parent | 26f725efc235b282e20aa678f8e683a014920b71 (diff) | |
| download | coreboot-22e0c560bb565642d52e4e0f8bab000c8d06f0b8.tar.xz | |
riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md
Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions