summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-12-11 17:20:16 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-12-14 11:05:51 +0000
commit233ae1919b72434ca6cd783c9a946d32953bc7e9 (patch)
tree52034859f35a1ab58e6f870b2b040e33d8eeda5d /src/soc/intel
parent68cf57cf33141edcc8b4b1250b099884e0553457 (diff)
downloadcoreboot-233ae1919b72434ca6cd783c9a946d32953bc7e9.tar.xz
soc/intel/braswell: Clean up devicetree settings
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/braswell/chip.c12
-rw-r--r--src/soc/intel/braswell/chip.h12
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c10
3 files changed, 11 insertions, 23 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 25965a04a7..2adda5494f 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -81,9 +81,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->ChvSvidConfig = config->ChvSvidConfig;
params->DptfDisable = config->DptfDisable;
params->PcdEmmcMode = config->PcdEmmcMode;
- params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
- params->PcdDispClkSsc = config->PcdDispClkSsc;
- params->PcdSataClkSsc = config->PcdSataClkSsc;
+ params->PcdUsb3ClkSsc = 1;
+ params->PcdDispClkSsc = 1;
+ params->PcdSataClkSsc = 1;
params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
@@ -115,14 +115,14 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5;
params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5;
- params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
+ params->PcdSataInterfaceSpeed = 3;
params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
- params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
+ params->PcdPcieRootPortSpeed = 0;
params->PcdPchSsicEnable = config->PcdPchSsicEnable;
params->PcdLogoPtr = config->PcdLogoPtr;
params->PcdLogoSize = config->PcdLogoSize;
- params->PcdRtcLock = config->PcdRtcLock;
+ params->PcdRtcLock = 0;
params->PMIC_I2CBus = config->PMIC_I2CBus;
params->ISPEnable = config->ISPEnable;
params->ISPPciDevConfig = config->ISPPciDevConfig;
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 99a1f309ba..c27ee49ae1 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -41,7 +41,6 @@ enum usb_comp_bg_value {
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
- uint8_t clkreq_enable;
enum serirq_mode serirq_mode;
@@ -75,14 +74,9 @@ struct soc_intel_braswell_config {
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during MemoryInit.
*/
- uint16_t PcdMrcInitTsegSize;
- uint16_t PcdMrcInitMmioSize;
uint8_t PcdMrcInitSpdAddr1;
uint8_t PcdMrcInitSpdAddr2;
uint8_t PcdIgdDvmt50PreAlloc;
- uint8_t PcdApertureSize;
- uint8_t PcdGttSize;
- uint8_t PcdLegacySegDecode;
uint8_t PcdDvfsEnable;
uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */
@@ -110,9 +104,6 @@ struct soc_intel_braswell_config {
uint8_t ChvSvidConfig;
uint8_t DptfDisable;
uint8_t PcdEmmcMode;
- uint8_t PcdUsb3ClkSsc;
- uint8_t PcdDispClkSsc;
- uint8_t PcdSataClkSsc;
uint8_t Usb2Port0PerPortPeTxiSet;
uint8_t Usb2Port0PerPortTxiSet;
uint8_t Usb2Port0IUsbTxEmphasisEn;
@@ -137,14 +128,11 @@ struct soc_intel_braswell_config {
uint8_t Usb3Lane1Ow2tapgen2deemph3p5;
uint8_t Usb3Lane2Ow2tapgen2deemph3p5;
uint8_t Usb3Lane3Ow2tapgen2deemph3p5;
- uint8_t PcdSataInterfaceSpeed;
uint8_t PcdPchUsbSsicPort;
uint8_t PcdPchUsbHsicPort;
- uint8_t PcdPcieRootPortSpeed;
uint8_t PcdPchSsicEnable;
uint32_t PcdLogoPtr;
uint32_t PcdLogoSize;
- uint8_t PcdRtcLock;
uint8_t PMIC_I2CBus;
uint8_t ISPEnable;
uint8_t ISPPciDevConfig;
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index a82a4abc28..37ee93cd24 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -113,14 +113,14 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd
config = config_of(dev);
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
- upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0;
- upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
+ upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0;
+ upd->PcdMrcInitMmioSize = 0x800;
upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;
upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
- upd->PcdApertureSize = config->PcdApertureSize;
- upd->PcdGttSize = config->PcdGttSize;
- upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
+ upd->PcdApertureSize = 2;
+ upd->PcdGttSize = 1;
+ upd->PcdLegacySegDecode = 0;
upd->PcdDvfsEnable = config->PcdDvfsEnable;
upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
}