diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-11-08 15:48:14 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-11-13 16:32:33 +0000 |
| commit | 25b387a50b25ceaaca29cf94eb02582a0d0e390a (patch) | |
| tree | b0451ee6189ebeb794b573fe029691a3daa2d5bb /src/soc/intel | |
| parent | 98456f4ee6e1d7df2863e2fafe8e505522a48da8 (diff) | |
| download | coreboot-25b387a50b25ceaaca29cf94eb02582a0d0e390a.tar.xz | |
soc/intel/cannonlake: Remove SmbusEnable
Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2deb35fdb8..015133e9ed 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -166,9 +166,6 @@ struct soc_intel_cannonlake_config { * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; - /* SMBus */ - uint8_t SmbusEnable; - /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 8506214425..8f6fa2ff54 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -66,6 +66,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -73,7 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) soc_memory_init_params(m_cfg, config); /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; + if (!smbus) + m_cfg->SmbusEnable = 0; + else + m_cfg->SmbusEnable = smbus->enabled; /* Set debug probe type */ m_cfg->PlatformDebugConsent = config->DebugConsent; |